The present invention relates to data processing burst access techniques and, more particularly, to a burst access technique in which the size of the burst can be programmed and in which the processor does not monitor the number of transfers of data per burst.
In data processing systems, the transfer of data and instructions from processors to memories has been facilitated in recent years with a technique called burst access or burst transfer. In this technique, an initial address is specified and the system accesses consecutive address locations sequentially for the purpose of reading data therefrom or storing data therein. A controller, connected between a processor and a memory, is responsible for carrying out the burst access. The controller increments the addresses to generate new ones for which data is to be accessed.
If ten addresses are to be accessed and they are all sequential, only the first address need be specified in the burst mode. After that, the subsequent nine addresses are automatically accessed.
In certain prior art computer systems, the processor controls the burst mode transfers. The processor is aware of the length of data transfers within each burst and controls data transfer within that size restriction.
In other systems, however, the processor does not keep track of how many data transfers occur within a burst. Accordingly, it has been difficult heretofore to determine when a burst terminates. In these cases, the controller is responsible for keeping track of how many data transfers have taken place.
The problem has arisen that the controller must communicate with the processor to inform it that no additional data transfers can be requested at a certain point after the burst has terminated. The problem is particularly troublesome when a processor cannot handle more than a fixed number of burst transfers. In cases where the processor does not keep track of the number of transfers under burst access and cannot handle more than a predetermined number of transfers, the problem has heretofore eluded solution.
It would be advantageous to allow a controller to keep track of the number of transfers within a burst and to inform the processor when to cease requesting transfers.
It would also be advantageous to provide a system for aligning a new burst with a complete number of transfers automatically, so that the efficiency of data access operations can be maximized.
It would also be advantageous to provide for a masking function to allow only certain bits to be compared.
It would also be advantageous to keep track of the maximum number of data transfers within a burst.
It would also be advantageous to provide a system for informing a processor that the maximum number of transfers under the current burst request has been performed and that a new address with a new burst request must be made by the processor to continue data transfer in the burst mode.